AMBA 101.

Advanced Microcontroller Bus Architecture by ARM

• ASB - advanced system bus
• APB - advanced peripheral bus (used for low power peripheral modules)
• AHB - advanced high performance bus
• Arbitration
• round robin priority scheme (default priority: master0)
• fair chance
• random access
• high priority
• burst transfer 
• undefined length or 4, 8, 16 in length
• fixed address, incremental address, or wrap address for cache line
• split transactions
• multiple masters
• through a central arbiter
• through  multiple slave level arbiters in multi-layer AHB-Lite system.
• masters could be DMA controller, a peripheral core master interface, etc.
• wider address bus, separate read or write data bus
• larger data paths (multiplexed, not tri-state)
• pipelined operation
• wait-state insertion
• data-valid signal HREADY
• AHB and APB is linked through a bridge that acts as the master to the peripheral bus slave devices.

AHB Signals

• General
• HCLK
• HRESET
• Arbiter / Master
• HBUSREQ (one from each master) 
• HGRANT (one for each master)
• Master / Slave
• HRESP ([1:0] or [0] in AHB-Lite)
• 00 - OKAY
• 01 - ERROR
• 10 - RETRY
• 11 - SPLIT
• HREADY (used by slave to insert wait state)
• when it's low (from slave) all control signals shall hold their values.
• HTRANS[1:0] (set according to RD or WR)
• 00 - IDLE
• 01 - BUSY (master can use BUSY to insert wait state during bursting)
• 10 - NONSEQ
• First transfer of an AHB sequence is always NONSEQ
• 11 - SEQ
• All transfer following the first shall be SEQ in nature.
• HWRITE
• HADDR [31:0] (muxed from individual masters to slaves and address decoder)
• HRDATA / HWDATA
• Slave / Arbiter
• HMASTER [3:0] / HMASTLOCK - from arbiter
• HSPLIT# [15:0] - one from each slave
• Address Decoder / Slave
• HSEL# (one for each slave unit)
• More from Masters to Slave
• HSIZE[2:0]
• HBURST[2:0]
• 4, 8, 16 in size
• incremental
• wrapping
• 000 - single
• 001 - INCR
• 010 - WRAP4
• 011 - INCR4
• 100 - WRAP8
• 101 - INCR8
• 110 - WRAP16
• 111 - INCR16
• HPROT[3:0] - protection control
• HLOCK# - locked transfer, one from each master
• lowered during the last transfer of an AHB sequence
• Example Auxilary Signals for AHB Masters
• REQ_VLD - input to bus master, asserted when HBUSREQ is asserted
• WR - input to bus master, high when HWRITE is high
• RD -  input to bus master, high when HWRITE is low
• IN_ADDR[31:0] - input to bus master, used to decide HADDR[31:0]
• IN_DATA[31:0]
• LEN#
• LAST
• OUT_DATA[31:0] - output from bus master
• REQ_WR_DATA - output from bus master
• It shall be high when (REQ_ADDR & WR) to ensure data shall be put on data bus one cycle after address is on.
• When REQ_WR_DATA ==1, IN_DATA will be put to data bus in next cycle.
• REQ_RD_DATA - output from bus master
• It shall be high when it's a read transfer and HREADY == 1.
• REQ_ADDR - output from bus master
• It shall be high when (HREADY & HGRANT) to ensure master can put address in next cycle.
• When REQ_ADDR == 1, IN_ADDR will be put to address bus in next cycle.

AHB Phases

• address/control 
• phase data phase

AHB Protocols

1. bus master sends HBUSREQ to arbiter and an address, decoded by central decoder to provide a dedicated HSEL to selected slave unit.
2. Slaves should only sample address when both HSEL and HREADY are high.
3. If the slave is under re-configuration or needs to terminate a transaction, it saves the Hmaster number, and sends RETRY or SPLIT to arbiter and arbiter remove the requesting master from list until the targeted slave de-assert Hsplit. If RETRY is sent, the transaction is dropped.
4. When the slave is ready, it signals the arbiter with the saved master number and the arbiter grants the bus access to the master to restart the transaction.
5. No master can have more than one pending split transaction.
6. Otherwise, master gets Hgrant and lock the bus. 
7. During burst mode (size indicated by HBURST[2:0]), master can insert wait state by sending HTRANS == BUSY. The slave has to send immediate OKAY in next cycle as for the case of IDLE and ignore the transfer.
8.  First burst cycle is always NONSEQUENTIAL.
9. HADDR must be aligned to the HBURST size, that is, A[1:0] == 2'b00 in word transfer and A[0] == 1'b0 in halfword transfer.
10. If a master is granted the bus without requesting it, it has to drive the transfer type IDLE.

APB Signals

• PCLK
• PRESETn - active LOW
• PSEL# - APB select
• PEN or PENABLE - APB strobe
• PADDR[31:0] - Address bus
• PWRITE - Transfer direction
• PWDATA[31:0] - Write data bus (can be 8, 16, 32 bit)
• PRDATA[31:0]  - Read data bus
• PREADY

APB States

• IDLE       : (~PSEL & ~PEN)
• SETUP    : (  PSEL & ~PEN)
• ACCESS : (  PSEL &   PEN)

AHB/APB Bridge Approach

• Cross clock domain data transfer
• handshake signaling method (double stage synchronizer)
• asynchronous FIFO

ASB Signals

• AGNT# - Bus grant
• AREQ# - Bus request
• BA[31:0] - Address bus
• BCLK - Bus clock
• BD[31:0] - Data bus
• BERROR - Error response
• BLAST - Last response
• BLOK - Locked transfer
• BnRES - Reset
• BPROT[1:0] - Protection control
• BSIZE[1:0] - Transfer size
• BTRAN[1:0] - Transfer bype (driven when AGNT# is asserted)
• ADDRESS-ONLY
• NON-SEQUENTIAL
• SEQUENTIAL
• BWAIT - Wait response
• BWRITE - Transfer direction
• DSEL# - Slave select