Circuit Playground Sites.

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• UVM simulator EDA playground

AMBA 101.

Advanced Microcontroller Bus Architecture by ARM

• ASB - advanced system bus
• APB - advanced peripheral bus (used for low power peripheral modules)
• AHB - advanced high performance bus
• Arbitration
• round robin priority scheme (default priority: master0)
• fair chance
• random access
• high priority
• burst transfer 
• undefined length or 4, 8, 16 in length
• fixed address, incremental address, or wrap address for cache line
• split transactions
• multiple masters
• through a central arbiter
• through  multiple slave level arbiters in multi-layer AHB-Lite system.
• masters could be DMA controller, a peripheral core master interface, etc.
• wider address bus, separate read or write data bus
• larger data paths (multiplexed, not tri-state)
• pipelined operation
• wait-state insertion
• data-valid signal HREADY
• AHB and APB is linked through a bridge that acts as the master to the peripheral bus slave devices.

AHB Signals

• General
• HCLK
• HRESET
• Arbiter / Master
• HBUSREQ (one from each master) 
• HGRANT (one for each master)
• Master / Slave
• HRESP ([1:0] or [0] in AHB-Lite)
• 00 - OKAY
• 01 - ERROR
• 10 - RETRY
• 11 - SPLIT
• HREADY (used by slave to insert wait state)
• when it's low (from slave) all control signals shall hold their values.
• HTRANS[1:0] (set according to RD or WR)
• 00 - IDLE
• 01 - BUSY (master can use BUSY to insert wait state during bursting)
• 10 - NONSEQ
• First transfer of an AHB sequence is always NONSEQ
• 11 - SEQ
• All transfer following the first shall be SEQ in nature.
• HWRITE
• HADDR [31:0] (muxed from individual masters to slaves and address decoder)
• HRDATA / HWDATA
• Slave / Arbiter
• HMASTER [3:0] / HMASTLOCK - from arbiter
• HSPLIT# [15:0] - one from each slave
• Address Decoder / Slave
• HSEL# (one for each slave unit)
• More from Masters to Slave
• HSIZE[2:0]
• HBURST[2:0]
• 4, 8, 16 in size
• incremental
• wrapping
• 000 - single
• 001 - INCR
• 010 - WRAP4
• 011 - INCR4
• 100 - WRAP8
• 101 - INCR8
• 110 - WRAP16
• 111 - INCR16
• HPROT[3:0] - protection control
• HLOCK# - locked transfer, one from each master
• lowered during the last transfer of an AHB sequence
• Example Auxilary Signals for AHB Masters
• REQ_VLD - input to bus master, asserted when HBUSREQ is asserted
• WR - input to bus master, high when HWRITE is high
• RD -  input to bus master, high when HWRITE is low
• IN_ADDR[31:0] - input to bus master, used to decide HADDR[31:0]
• IN_DATA[31:0]
• LEN#
• LAST
• OUT_DATA[31:0] - output from bus master
• REQ_WR_DATA - output from bus master
• It shall be high when (REQ_ADDR & WR) to ensure data shall be put on data bus one cycle after address is on.
• When REQ_WR_DATA ==1, IN_DATA will be put to data bus in next cycle.
• REQ_RD_DATA - output from bus master
• It shall be high when it's a read transfer and HREADY == 1.
• REQ_ADDR - output from bus master
• It shall be high when (HREADY & HGRANT) to ensure master can put address in next cycle.
• When REQ_ADDR == 1, IN_ADDR will be put to address bus in next cycle.

AHB Phases

• address/control 
• phase data phase

AHB Protocols

1. bus master sends HBUSREQ to arbiter and an address, decoded by central decoder to provide a dedicated HSEL to selected slave unit.
2. Slaves should only sample address when both HSEL and HREADY are high.
3. If the slave is under re-configuration or needs to terminate a transaction, it saves the Hmaster number, and sends RETRY or SPLIT to arbiter and arbiter remove the requesting master from list until the targeted slave de-assert Hsplit. If RETRY is sent, the transaction is dropped.
4. When the slave is ready, it signals the arbiter with the saved master number and the arbiter grants the bus access to the master to restart the transaction.
5. No master can have more than one pending split transaction.
6. Otherwise, master gets Hgrant and lock the bus. 
7. During burst mode (size indicated by HBURST[2:0]), master can insert wait state by sending HTRANS == BUSY. The slave has to send immediate OKAY in next cycle as for the case of IDLE and ignore the transfer.
8.  First burst cycle is always NONSEQUENTIAL.
9. HADDR must be aligned to the HBURST size, that is, A[1:0] == 2'b00 in word transfer and A[0] == 1'b0 in halfword transfer.
10. If a master is granted the bus without requesting it, it has to drive the transfer type IDLE.

APB Signals

• PCLK
• PRESETn - active LOW
• PSEL# - APB select
• PEN or PENABLE - APB strobe
• PADDR[31:0] - Address bus
• PWRITE - Transfer direction
• PWDATA[31:0] - Write data bus (can be 8, 16, 32 bit)
• PRDATA[31:0]  - Read data bus
• PREADY

APB States

• IDLE       : (~PSEL & ~PEN)
• SETUP    : (  PSEL & ~PEN)
• ACCESS : (  PSEL &   PEN)

AHB/APB Bridge Approach

• Cross clock domain data transfer
• handshake signaling method (double stage synchronizer)
• asynchronous FIFO

ASB Signals

• AGNT# - Bus grant
• AREQ# - Bus request
• BA[31:0] - Address bus
• BCLK - Bus clock
• BD[31:0] - Data bus
• BERROR - Error response
• BLAST - Last response
• BLOK - Locked transfer
• BnRES - Reset
• BPROT[1:0] - Protection control
• BSIZE[1:0] - Transfer size
• BTRAN[1:0] - Transfer bype (driven when AGNT# is asserted)
• ADDRESS-ONLY
• NON-SEQUENTIAL
• SEQUENTIAL
• BWAIT - Wait response
• BWRITE - Transfer direction
• DSEL# - Slave select

ARM 101.

• Before 2004
• ARM7TDMI
• ARM9E
• ARM11

• 2004-2009
• Cortex-M1
• Cortex-M3
• Cortex-A8
• Cortex-A9
• Cortex-R4
• Cortex-M0
• Cortex-A5

• 2009-2012
• Cortex-M0+
• Cortex-R5
• Cortex-R7
• Cortex-A15
• Cortex-A7

• 2012-2016
• Cortex-M7
• Cortex-A12
• Cortex-A53
• Cortex-A57
• Cortex-A17
• Cortex-A72

• M Series - Microcontroller applications
• main-stream market
• Low-power
• short pipeline (as low as 2 stages in M+, 3 stages in M0, M3, M4, 6 stages in M7)
• slower clock speed due to short pipelines (say, 100MHz)
• quick and deterministic interrupt responses with closely coupled execution control
• Built-in interrupt management controller NVIC (Nested Vectored Interrupt Controller)
• C-language friendly
• used in sensors, wireless communication chipsets, mixed signal ASICs/ASSPs, or as in subsystems to assist comples application processors/SoC products.

• R Series - High performance Real-time systems
• real time fast data-crunching for modern IoT applications.
• fairly high clock speed (500 MHz to 1 GHz)
• very responsive to hardware events
• cache memories
• tightly coupled memories for deterministic behavior for interrupt handling
• higher reliability features (ECC for memory systems, dual-core lock-step)
• used in hard drive controllers, wireless baseband controllers, modem, automotive and industrial controllers.

• A Series - High end Application processors
• support Android, Linux, Windows, iOS
• longer processor pipeline
• high clock frequency (>1 GHz)
• MMU to support virtual memory addressing
• optional Java support
• secure program excution environment (TrustZone)
• used in smart phones, tablets, TVs, green servers.
• not for real time rapid responses.

• SecurCore Series - for security-sensitive products with temp resistance features, such s SIM cards, banking/payment systems and some electronic ID cards.

• ARM Info Center
• ARM M0 ISA
• ARM M3 ISA and Architecture
• M3/M4 Instruction Set Manual
• ARM-M7 Architecture
• ARM7 and Thumb2 Instruction Set
• ARM7 and Thumb2 Instruction Set QR
• ARM ISA
• ARM ISA Slides
• Cortex-A Programmer's Guide
• ARM Architecture Overview
• ARM Architecture Reference Manual

OVM 101 - part 2.

Test Environment Nitty Gritty Code

• Configuration - Connecting virtual interface from top level to DUT.
• Use configuration table to store the wrapper(s) of virtual interface properties.
• This way, the test bench can be used with different configurations, changing wrappers.
• Configuration using "set_config_object" and "get_config_object" overrides top-down.
  ( from ovm_test -> ovm_env -> ovm_component)

// Top level "module" contains class based test environment
//        and structural interface that drives DUT (module)
module top;

import ovm_pkg::*;
import my_pkg::*;

...
dut_if dut_if_inst1 ();
dut dut_inst0 (._if (dut_if_inst1) );

initial begin: blk
    dut_if_wrapper if_wrapper = new ("if_wrapper", dut_if_inst1);
                   // path  field_name        value      0: don't clone
    set_config_object("*", "dut_if_wrapper", if_wrapper, 0);

    run_test ("my_test_set");
end

endmodule : top

class dut_if_wrapper extends ovm_object;

    virtual dut_if dut_vi;
    function new (string s, virtual dut_if if_arg); 
        super.new(s);
        dut_vi = if_arg;
    endfunction : new

endclass : dut_if_wrapper

// ovm classes
// usually classes of test environment that includes fixed test bench
// and variable test sets

`include "ovm_macros.svh"

package my_package;
import ovm_pkg::*;

// Fixed test environment
class my_test_env extends ovm_env;
    `ovm_component_utils (my_test_env)

    virtual dut_if dut_virtual_if_inst;

    // constructor
    function new (string s, ovm_component inst_parent);
        super.new (s, inst_parent);
    endfunction : new

    function void build;
        super.build ();
        begin
            ovm_object obj;
            dut_if_wrapper if_wrapper; 
            get_config_object("dut_if_wrapper", obj, 0);
            assert( $cast(if_wrapper, obj) );
            dut_virtual_if_inst = if_wrapper.dut_vi;
        end
    endfunction : build

    task run;
        #10 dut_virtual_if_inst.data = 0;
        #10 dut_virtual_if_inst.data = 1;
        #10 ovm_top.stop_request();
    endtask : run

endclass : my_test_env

class my_test_set extends ovm_test;
    `ovm_component_utils (my_test_set)

    my_test_env my_test_env_handle;

    // constructor
    function new(string s, ovm_component inst_parent);
        super.new(s, inst_parent);
    endfunction : new

    function void build;
        super.build();
        my_test_env_handle = my_test_env::type_id::create
            ("my_test_env_handle", this);
    endfunction : build

endclass : my_test_set

// interface dut_if(); -> between test components and DUT
interface dut_if ();

    logic clock, reset;
    logic data_input;

endinterface : dut_if

// Design under test
module DUT (dut_if _if);

    always @ (posedge _if.clock)
    begin
    end

endmodule : dut

// Higher level overriding lower level configuration
// Overriding Example:
// in ovm_test
set_config_object ("*", "data", x);
// in ovm_env
get_config_object ("opt", y);
set_config_object ("*", "data", y);
// in ovm_component
get_config_object ("data", obj); // obj = x

OVM 101.

Test Environment Structure

diagram

// Top level "module" contains class based test environment
//        and structural interface that drives DUT (module)
module top;

import ovm_pkg::*;
import my_pkg::*;

...
dut_if dut_if_inst0 ();
dut dut_inst0 (._if (dut_if_inst0) );

initial
begin
    run_test ("my_test_set");
end

endmodule : top

// ovm classes
// usually classes of test environment that includes fixed test bench
// and variable test sets

`include "ovm_macros.svh"

package my_package;
import ovm_pkg::*;

// Fixed test environment
class my_test_env extends ovm_env;
    `ovm_component_utils (my_test_env)

    // constructor
    function new (string s, ovm_component inst_parent);
        super.new (s, inst_parent);
    endfunction : new

    function void build;
        super.build ();
    endfunction : build

    task run;
        #10 ovm_top.stop_request();
    endtask : run

endclass : my_test_env

class my_test_set extends ovm_test;
    `ovm_component_utils (my_test_set)

    my_test_env my_test_env_handle;

    // constructor
    function new(string s, ovm_component inst_parent); 
        super.new(s, inst_parent);
    endfunction : new

    function void build;
        super.build();
        my_test_env_handle = my_test_env::type_id::create 
            ("my_test_env_handle", this);
    endfunction : build

endclass : my_test_set

// interface dut_if(); -> between test components and DUT
interface dut_if ();
...
endinterface : dut_if

// Design under test
module DUT (dut_if _if); 
endmodule : dut

UVM/OVM primer.

Basic Concepts:

• Constrained random, coverage-driven verification
• Configurable, flexible, test benches
• Verification IP reuse

• Separation of tests from test bench
• TLM communication
• Layered sequential stimulus
• Standardized messaging
• Register layer (UVM)

UVM Class Hierarchy

• uvm_object

OVM Class Hierarchy

• ovm_object
• obm_report_object
• ovm_component
• ovm_env
• ovm_test
• ovm_agent
• ovm_sequencer
• ovm_driver
• ovm_monitor
• ovm_scoreboard
• ovm_agent usually contains driver / monitor and sequencer

Prerequisite:

• Verification Planning
• Constrained Random Verification
• SystemVerilog
• UVM/OVM Class Library, OOP, TLM

Useful Links:

• First Program
• Connecting Env to DUT
• Connecting Components
• Transactions
• Sequences and Tests
• Mnitors and Subscribers
• Reporting
• UVM tutorial
• OVM tutorial
• OVM Class Reference Online
• OVM Class Reference PDF

FIFO

Asynchronous FIFO:

reg clk1; // write clock

reg clk2; // read clock

reg full_flag;

reg empty_flag;

// Set the Direction Signal to High when Write_address (Write_pointer ) is less than 

// Read_address( or Read_pointer ) &&
// i.e. (Write_pointer > Read_pointer ) then Direction = 1;

// Reset the Direction Signal to Low when Write_address( or Write_pointer ) is greater than 

// Read_address( or Read_pointer )
// i.e. ( Write_pointer < Read_pointer ) then Direction = 0;

// Case 1: ( Full Flag )
// Assert status Full flag When Direction Signal == 1 && ( Write_pointer == Read_pointer )
if ( Direction == 1 && ( Write_pointer == Read_pointer ) )  full_flag = 1;

else full_flag = 0;


// Case 2: ( Empty Flag )
// Assert status Empty flag When Direction Signal == 0 && ( Write_pointer == Read_pointer )

if ( Direction == 0 && ( Write_pointer == Read_pointer ) ) empty_flag = 1;

else empty_flag = 0;


// When Comparing Write_pointer && Read_pointer to assert Empty or Full
// one pointer has to be synchronized to the other's clock domain
// watch for the 2 clock delay and align with the direction to avoid 

// overflow and underflow in FIFO

// In general, write pointer should be delayed and behind the read pointer to

// avoid overwriting unread data.
// that is,  compare: if (Write_pointer == two_clk_delay_Read_pointer )

// Use buffer management techniques if desired.

ASIC Examples.

• Full adder can be implemented by two half adder; a half adder can be implemented by a XOR and AND gate. XOR and AND gate can be implemented by 2:1 MUX.
  
  Full adder can be implemented using 8 muxes.
• Design a combinational circuit which counts the number of 1s in a 7-bit input.
• Design a divide by 3 counter (frequency by 3 divider). Bonus for 50% duty cycle output. (Answer)
• How to fix setup time violation and hold time violation.
• Complete the c function that uses recursion to determine if the string is a palindrome.

• How to minimize the power dissipation of an ASIC chip.

• Use full adder to detect how many logic 1's there are in a 8-bit input data.

• Design state machine to test 10110101, how many flip-flops will be used?

• Design a circuit that would count 1 every time when another counter counts from 0 to 255. One of the counter is working at higher frequency than the other.

• Write Verilog for a 3 to 1 arbiter, with a priority client and 2 other clients in a round robin manner.

• What is Moore FSM and Mealy FSM?

• Write a Verilog to convert JK Flip-flop to D Flip-Flop.

• What is the basic pipeline stages in computer architecture.

• Which gate would you prefer in a design NAND or NOR and why?

• Write Verilog code to swap data with and without a temporary register.

• How to design clock gating for an 8-bit counter

• What are the different ways to design clock gating in order to reduce power consumption?

• Design a block with one data input and one clock input. The output is '1' when '0110' is detected in input and '0' otherwise.

• Basic steps of synthesis.

• How to decide the FIFO size when input rate is N and output rate is M.

• What would be the behavior of a CMOS inverter if the NMOS and PMOS are interchanged.

• Verilog code to design asynchronous FIFO.

• FIFO synchronized and asynchronized.

• Setup up time and hold time calculation.

• What is the process of designing a FPGA.

• Design a UVM driver

• How do you combine states in a state machine? Do you save anything?

• How to print out elements on 1/8th of the circumference of a circle?

• How to get the second largest number in an unsorted array?

• Basic DFT flow.

• Cross domain clock (or clock domain crossing) design example.

• Write verilog code of D-Latch

• Use two 2-bit comparators to implement a 4-bit comparator and reduce the delay to one unit. Compare '0100_0000_01' and use the simplest RTL design to get the length (which is 9)

• Write a FSM to detect the sequence 101011

• How to design AND and OR gates with 2x1 Mux?

• How many data bits are needed to represent A*B+C, all 8-bit unsigned.

• What is the relationship between read and write clocks for different data widths in a FIFO?

• Explain setup time and hold time on a registered path with clock skew.

• Pipeline stages in MIPS.

• What is RAW, WAW and WAR hazards and how to solve them in linear and OoO pipelines?

• Multi Clock domain FIFO design.

• Cache stages