ASIC Examples.

• Full adder can be implemented by two half adder; a half adder can be implemented by a XOR and AND gate. XOR and AND gate can be implemented by 2:1 MUX.
  
  Full adder can be implemented using 8 muxes.
• Design a combinational circuit which counts the number of 1s in a 7-bit input.
• Design a divide by 3 counter (frequency by 3 divider). Bonus for 50% duty cycle output. (Answer)
• How to fix setup time violation and hold time violation.
• Complete the c function that uses recursion to determine if the string is a palindrome.

• How to minimize the power dissipation of an ASIC chip.

• Use full adder to detect how many logic 1's there are in a 8-bit input data.

• Design state machine to test 10110101, how many flip-flops will be used?

• Design a circuit that would count 1 every time when another counter counts from 0 to 255. One of the counter is working at higher frequency than the other.

• Write Verilog for a 3 to 1 arbiter, with a priority client and 2 other clients in a round robin manner.

• What is Moore FSM and Mealy FSM?

• Write a Verilog to convert JK Flip-flop to D Flip-Flop.

• What is the basic pipeline stages in computer architecture.

• Which gate would you prefer in a design NAND or NOR and why?

• Write Verilog code to swap data with and without a temporary register.

• How to design clock gating for an 8-bit counter

• What are the different ways to design clock gating in order to reduce power consumption?

• Design a block with one data input and one clock input. The output is '1' when '0110' is detected in input and '0' otherwise.

• Basic steps of synthesis.

• How to decide the FIFO size when input rate is N and output rate is M.

• What would be the behavior of a CMOS inverter if the NMOS and PMOS are interchanged.

• Verilog code to design asynchronous FIFO.

• FIFO synchronized and asynchronized.

• Setup up time and hold time calculation.

• What is the process of designing a FPGA.

• Design a UVM driver

• How do you combine states in a state machine? Do you save anything?

• How to print out elements on 1/8th of the circumference of a circle?

• How to get the second largest number in an unsorted array?

• Basic DFT flow.

• Cross domain clock (or clock domain crossing) design example.

• Write verilog code of D-Latch

• Use two 2-bit comparators to implement a 4-bit comparator and reduce the delay to one unit. Compare '0100_0000_01' and use the simplest RTL design to get the length (which is 9)

• Write a FSM to detect the sequence 101011

• How to design AND and OR gates with 2x1 Mux?

• How many data bits are needed to represent A*B+C, all 8-bit unsigned.

• What is the relationship between read and write clocks for different data widths in a FIFO?

• Explain setup time and hold time on a registered path with clock skew.

• Pipeline stages in MIPS.

• What is RAW, WAW and WAR hazards and how to solve them in linear and OoO pipelines?

• Multi Clock domain FIFO design.

• Cache stages