SystemVerilog Question.

• Automatic vs Static
  For a static task, multiple invocations of the same task will reference the same local variables. For an automatic task, the local variables will be unique to each invocation of the task. The function should be automatic so that there will be multiple memory allocations for the index variable to show increasing values instead of a single value.
• packed vs unpacked
  Unpacked array is an array with gap between variables.
• Join / Join_any / Join_none
  Join (and all done) / Join_any (or any done) / Join_none (none is done, non-blocking)
  (use "wait fork;" or implement watch_dog timer for "join_none" for synchronization)
• Wire vs Logic
  Logic and wire are almost the same except wire can be driven by multiple sources. Logic can only driven by single source.
• Virtual
  Means "abstract"