Basic Concepts:
- Constrained random, coverage-driven verification
- Configurable, flexible, test benches
- Verification IP reuse
- Separation of tests from test bench
- TLM communication
- Layered sequential stimulus
- Standardized messaging
- Register layer (UVM)
UVM Class Hierarchy
- uvm_object
OVM Class Hierarchy
- ovm_object
- obm_report_object
- ovm_component
- ovm_env
- ovm_test
- ovm_agent
- ovm_sequencer
- ovm_driver
- ovm_monitor
- ovm_scoreboard
- ovm_agent usually contains driver / monitor and sequencer
Prerequisite:
- Verification Planning
- Constrained Random Verification
- SystemVerilog
- UVM/OVM Class Library, OOP, TLM
Useful Links:
- First Program
- Connecting Env to DUT
- Connecting Components
- Transactions
- Sequences and Tests
- Mnitors and Subscribers
- Reporting
- UVM tutorial
- OVM tutorial
- OVM Class Reference Online
- OVM Class Reference PDF
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