FIFO

Asynchronous FIFO:

reg clk1; // write clock

reg clk2; // read clock

reg full_flag;

reg empty_flag;

// Set the Direction Signal to High when Write_address (Write_pointer ) is less than 

// Read_address( or Read_pointer ) &&
// i.e. (Write_pointer > Read_pointer ) then Direction = 1;

// Reset the Direction Signal to Low when Write_address( or Write_pointer ) is greater than 

// Read_address( or Read_pointer )
// i.e. ( Write_pointer < Read_pointer ) then Direction = 0;

// Case 1: ( Full Flag )
// Assert status Full flag When Direction Signal == 1 && ( Write_pointer == Read_pointer )
if ( Direction == 1 && ( Write_pointer == Read_pointer ) )  full_flag = 1;

else full_flag = 0;


// Case 2: ( Empty Flag )
// Assert status Empty flag When Direction Signal == 0 && ( Write_pointer == Read_pointer )

if ( Direction == 0 && ( Write_pointer == Read_pointer ) ) empty_flag = 1;

else empty_flag = 0;


// When Comparing Write_pointer && Read_pointer to assert Empty or Full
// one pointer has to be synchronized to the other's clock domain
// watch for the 2 clock delay and align with the direction to avoid 

// overflow and underflow in FIFO

// In general, write pointer should be delayed and behind the read pointer to

// avoid overwriting unread data.
// that is,  compare: if (Write_pointer == two_clk_delay_Read_pointer )

// Use buffer management techniques if desired.